Spintec laboratory is opening a postdoctoral / engineer researcher position in the frame of the regional project ATEMIS.
MRAM are currently introduced at back-end-of-line (BEOL), and excelling on process control and yield performances are crucial for High Volume Manufacturing, as the largest part of the manufacturing process is already executed. Indeed, when the wafer is ready to be tested with BEOL MRAM, the fab process cost ratio is at 70-90% of the final chip cost. Therefore, the designed test flow of eMRAM chip should be at the same time cost efficient (high throughput) and it should consider MRAM specificities at each test stages (MTJ, arrays and chip). A metrology flow smartly designed at the utmost with consideration of the Magnetic Tunnel Junctions (MTJ) and writing mechanisms physics involved (STT, SOT…) are key to ensure that chip product meet the target specifications.
The objective of ATEMIS addresses these technological challenges related to the industrial implementation of an MRAM automatic test equipment in the back-end phase (at wafer sort and final test positions). It will help the semiconductor industry to test MRAM-based chips with a level of performance equivalent to that seen in other memory technologies. This project will be conducted in collaboration with Hprobe (MRAM prober developer) and Antaios (SOT-MRAM developer) startup companies.
What you will do:
You will start by reviewing and classifying the device failures mechanisms occurring in MRAM arrays to explore on how these mechanisms can be controlled and monitored at the single MTJ cells level.
You will contribute to fabricating scaled single-cell STT- and SOT-MRAM devices to be used as test vehicle for the development of new testing methodologies of MRAM devices. The fabrication of the test vehicle will be done in our academic clean room facilities (PTA).
You will conduct electrical characterization experiments and parametric studies using MRAM wafer level tester with the objective to develop novel methods and protocols to extract MRAM physical and magnetic parameters while improving testing speed. These methods will smartly combine magnetic fields and electrical impulsions, keeping in mind tools industrial constraints and further application to MRAM large arrays. The speed gain will be further demonstrated on memory arrays.
Finally, you will contribute to validate and implement these novel methodologies on industrial automated test equipment (ATE) developed by Hprobe, demonstrating the possibility to accelerate the wafer sort in the back-end phase of MRAM chips.
You will join the “MRAM team” of Spintec for a 20 months-long position (possibly extended to 24 months), expected to start on March-April 2022.
You should have experience with magnetism and spintronics. A previous experience in nanofabrication and MRAM characterization is beneficial.
Candidates should send a CV and a letter of motivation to Kevin Garello.
Further information about Spintec laboratory www.spintec.fr