PhD thesis defense : Design of an Innovative Asynchronous, Non-Volatile Integrated Circuit for Space Applications


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On Monday, the 18th Of September 2017 at 14h00, Jérémy LOPES from DRF/INAC/SPINTEC, will defend his PhD thesis entitled “Design of an Innovative Asynchronous, Non-Volatile Integrated Circuit for Space Applications”
Place : LIRMM, 161 rue Ada 34095 Montpellier, salle de séminaire du LIRMM

Today, there are several ways to develop microelectronic circuits adapted for space applications that meet the harsh constraints of immunity towards radiation, whether in terms of technical design or manufacturing process. The aim of this doctorate is on the one hand to combine several novel techniques of microelectronics to design architectures adapted to this type of application, and on the other hand to incorporate non-volatile magnetic components inherently robust to radiation. Such an assembly would be quite innovative and would benefit without precedent, in terms of surface, consumption, robustness and cost.

In contrast with synchronous circuit designs that rely on a clock signal, asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. Furthermore, by avoiding the use of a clock, asynchronous circuits have relatively low power consumption. Asynchronous circuits are generally designed to operate based on events determined using a specific handshake protocol. The basic circuit element of an asynchronous design is a circuit known as a C-element or Muller cell. This circuit includes a volatile latch for storing a state. Thus if the asynchronous circuit is powered down, the data stored by the various C-elements will be lost. An asynchronous pipeline is generally formed in stages, each stage comprising a half buffer formed of several C-elements.

For aviation and/or spatial applications, it would be desirable to provide an asynchronous circuit that is rendered robust against the effects of radiation. Indeed, the presence of ionising particles at high altitudes or in space can induce currents in integrated circuits that may be enough to cause a flip in the binary state held by one or more gates. This may cause the circuit to malfunction, known in the art as a single event upset (SEU). It has been proposed to provide dual modular redundancy (DMR) or triple modular redundancy (TMR) in an asynchronous circuit design in order to provide radiation protection. Such techniques rely on duplicating the circuit in the case of DMR, or triplicating the circuit in the case of TMR, and detecting a discordance between the outputs of the circuits as an indication of the occurrence of an SEU. A problem with the DMR technique is that it does not permit the error to be corrected, and thus when an error is detected, the circuit is simply reset. This adds a time delay, as the processing operation must be restarted. Furthermore, if SEUs occur at a relatively high rate, it may even be impossible for a processing operation to be completed before a reset is required. The TMR technique does allow the error to be corrected, for example by selecting the output value generated by two out of three of the circuits using a majority voter. However, a drawback with the TMR technique is that the surface area and power consumption of the circuit are increased by a factor of three.

The integration of inherently robust non-volatile components, such as Magnetic Tunnel Junctions (MTJ), the main element of MRAM memory, could lead to new ways of data retention in harsh environments. MTJ devices are constituted of ferromagnetic materials with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetisation and not in the form of an electric charge, which is an essential property for space applications. It is also widely recognised in the field of microelectronics that integrated circuits manufactured on SOI (Silicon On Insulator) substrates are more robust to radiation. This is due to the reduced active volume of the individual transistors as well as their isolation in regards to each other. The radiation-induced errors are very localized and therefore cannot be spread from one block to another, thanks to the insulation provided by the manufacturing process. Another important characteristic of SOI is its natural immunity towards latch-ups.

There is thus a need in the art for a circuit having relatively low surface area and power consumption, and that allows recovery following an SEU without requiring a reset and that has non-volatile characteristics. The objective of this doctorate is to combine all the above mentioned benefits by regrouping several methods of microelectronic design responding to the constraints of space applications into a novel architecture. A complete circuit has been created, designed, simulated, validated and sent to manufacturing in a 28nm FD-SOI process. This circuit is composed of an adder pipeline and a complex BIST (Build In Self-Test). When fabricated, this circuit will be tested. First a functional test will be realised, then laser pulses attacks will be performed and finally a heavy ions attack campaign.



Jury :
M. Jean-Michel PORTAL – Aix-Marseille Université, Rapporteur
M. Alex YAKOVLEV – Newcastle University, Rapporteur
M. David DANGLA – CNES, Examinateur
Mme Edith BEIGNé – CEA, Examinateur
M. Laurent DUSSEAU – Université de Montpellier, Examinateur
M. Lionel TORRES – Université de Montpellier, Directeur de these
M. Gregory DI PENDINA – UGA, CNRS, CEA/INAC/SPINTEC, Co-encadrant de these


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