The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications.
Hybrid CMOS/Magnetic design flow
Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.
Low-power logic circuits
One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.
While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.
Radiation hardening for space applications
The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques.
- Christophe LAYER : Research scientist
- François DUHEM: Research scientist
- Stephane GROS (2013-2014)
- Pierre PAOLI (2013-2014)
- Pierre VANHAUWAERT (2014-2017)
- Eldar ZIANBETOV (2014-2017)
- Kotb JABEUR (2013-2017)
- Virgile JAVERLIAC (2013-2014)
- Fabrice BERNARD-GRANGER (2013-2014)
- Yun YANG (2012-2013)
- Abdelilah MEJDOUBI (2010-2012)
- Mounia KHARBOUCHE (supervised by G. Di Pendina, R. Wacquez and J.M. Portal) (2016-2019)
- Rana ALHALABI (supervised by G. Di Pendina, E. Nowak and L. Prejbeanu) (2016-2019)
- Jeremy LOPES (supervised by G. Di Pendina, E. Beigne, D. Dangla and L. Torres) (2014-2017)
- Erya DENG (supervised by G. Prenat and L. Anghel) (2014-2017)
- Olivier GONCALVES (supervised by G. Prenat and B. Dieny) (2009-2012)
- Wei GUO (supervised by G. Prenat and B. Dieny) (2006 – 2010)
- Mourad El BARAJI (supervised by G. Prenat and B. Dieny) (2007-2009)
- NV-APROC, ANR (2019-2023)
- MISTRAL, ANR (2019-2023)
- HANS, UGA (2019-2022)
- ELECSPIN, ANR (2016-2020)
- GREAT, H2020 (2016-2019)
- MASTA, ANR (2016-2019)
- NOVELASIC, CEA-nanosciences (2015)
- MAD, CEA internal (2014-2018)
- SPOT, H2020 (2012-2015)
- MARS, ANR (2012-2015)
- DIPMEM, ANR (2012-2015)
- HYMAGINE, ERC Advanced grant (2010-2015)
- Toplink Innovation
- University of Brasov
- CEA Tech (Gardanne)
- EMSE (Gardanne)
- Tiempo Secure
- Dolphin Integration
- Thales TRT
- University of Newcastle
- EM Marin
- Spin Transfer Torque Magnetic Tunnel Junction for Single Event Effects mitigation in IC Design (July 23rd, 2020)
Due to its good radiation effects tolerance and its inherent non volatility, Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) is considered as a promising candidate for high-reliability electronics. A radiation tolerant circuit design suitable for space ...
- Lorena ANGHEL joins SPINTEC (June 05th, 2020)
We are pleased to announce the arrival on June 1st, 2020 at SPINTEC, within the Spintronics IC design team of Lorena ANGHEL, professor at Grenoble INP / PHELMA, currently deputy director in charge of Research ...
- Detection of Heating and Photocurrent attacks using Hybrid CMOS/STT-MRAM (March 26th, 2020)
Integrated Circuits (ICs) have to be protected against threatening environmental radiations and malicious perturbations. A large panel of countermeasures have been developed to answer the needs of this challenging field. This work proposes an innovative ...
- PhD defense – Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l’Internet des Objets (November 28th, 2019)
On Monday 9th of Decembre at 13h30 Mounia KHARBOUCHE-HARRARI, will defend her thesis, jointly carried out by IM2NP, CEA-Tech and SPINTEC, entitled : « Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l’Internet des ...
- Seminar – CMOS-compatible materials and processes for spintronic applications in 300mm R&D (October 21st, 2019)
On Wednesday October 23 at 14:00 we have the pleasure to welcome Maik Wagner-Reetz from Fraunhofer IPMS, Dresden. He will give us a seminar at CEA/SPINTEC, Bat 1005, room 445 entitled : CMOS-compatible materials and processes ...