The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications. The unique combination of advantages of spintronics devices (non-volatility associated with high speed and endurance, analogue capabilities, well controlled stochastic behavior…) allows intrinsically mixing the memory and logic functionalities (in Memory Computing). This opens the way towards new computing paradigms, beyond the standard Von-Newman architecture of computing systems. The most interesting applications addressed in the team are described below.
Hybrid CMOS/Magnetic design flow
Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.
Low-power logic circuits
One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.
IC Reliability: Hardware security & Radiation hardening
While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.
The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques targeting space applications.
Spiking Neural Networks are seen as a Key building block for strongly improving the energy efficiency of current AI applications and opening up new possibilities (in terms of unsupervised learning, recurrent networks, probabilistic inference, etc.). The scientific challenges to be tackled are the following: the first one is to define power-constrained learning and inference algorithms (online, supervised, unsupervised, probabilistic, etc.). The second one is to design a scalable and flexible SNN architecture, adaptable to the different above-mentioned algorithms, and fabricate that circuit in hybrid nanoscale CMOS and NVM technology, enabling very dense synaptic density. The last objective is to derive a principled toolchain for the algorithm, design, development, and integration of spiking neural networks for future adoption in industrial health and automotive embedded applications.
- NV-APROC, ANR (2019-2023) – MRAM-based Non-volatile Asynchronous Processor
- MISTRAL, ANR (2019-2023) – MRAM/CMOS Hybridization to secure cryptographic algorithms
- SPINBRAIN (2020-2022) – Spintronic-based Neural Network
- HANS, UGA (2019-2022) –
- ELECSPIN, ANR (2016-2020) – Electric-filed control of spin-based phenomena
- Christophe LAYER : Research scientist
- François DUHEM: Research scientist
- Mounia KHARBOUCHE (supervised by G. Di Pendina, R. Wacquez and J.M. Portal) (2016-2019)
- Rana ALHALABI (supervised by G. Di Pendina, E. Nowak and L. Prejbeanu) (2016-2019)
- Jeremy LOPES (supervised by G. Di Pendina, E. Beigne, D. Dangla and L. Torres) (2014-2017)
- Erya DENG (supervised by G. Prenat and L. Anghel) (2014-2017)
- Olivier GONCALVES (supervised by G. Prenat and B. Dieny) (2009-2012)
- Wei GUO (supervised by G. Prenat and B. Dieny) (2006 – 2010)
- Mourad El BARAJI (supervised by G. Prenat and B. Dieny) (2007-2009)
- Pierre VANHAUWAERT (2014-2017)
- Eldar ZIANBETOV (2014-2017)
- Kotb JABEUR (2013-2017)
- Virgile JAVERLIAC (2013-2014)
- Fabrice BERNARD-GRANGER (2013-2014)
- Yun YANG (2012-2013)
- Abdelilah MEJDOUBI (2010-2012)
- Stephane GROS (2013-2014)
- Pierre PAOLI (2013-2014)
- GREAT, H2020 (2016-2019)
- MASTA, ANR (2016-2019)
- NOVELASIC, CEA-nanosciences (2015)
- MAD, CEA internal (2014-2018)
- SPOT, H2020 (2012-2015)
- MARS, ANR (2012-2015)
- DIPMEM, ANR (2012-2015)
- HYMAGINE, ERC Advanced grant (2010-2015)
- Toplink Innovation
- University of Brasov
- CEA Tech (Gardanne)
- EMSE (Gardanne)
- Tiempo Secure
- Dolphin Integration
- Thales TRT
- University of Newcastle
- EM Marin
- Highlights of SPINTEC research in 2020 (December 10th, 2020)
The research highlights of SPINTEC over the year 2020 have been put together, and are available to download: http://www.spintec.fr/spintec-annual-booklets. This booklet contains the key facts of the lab over the period (contracts, new staff etc.), the ...
- Masters thesis projects for Spring 2021 (September 15th, 2020)
You find here the list of proposals for Master-2 internships to take place at Spintec during Spring 2021. In most cases, these internships are intended to be suitable for a longer-term PhD work. Interested Master-1 ...
- Review — Opportunities and challenges for spintronics in the microelectronics industry (August 19th, 2020)
The European consortium SpintronicFactory, largely supported by the French laboratories Spintec (Grenoble) and the CNRS-Thales Joint Lab (Palaiseau), publishes in the journal Nature Electronics an ambitious roadmap for spintronics. This discipline on the borderline between ...
- Spin Transfer Torque Magnetic Tunnel Junction for Single Event Effects mitigation in IC Design (July 23rd, 2020)
Due to its good radiation effects tolerance and its inherent non volatility, Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) is considered as a promising candidate for high-reliability electronics. A radiation tolerant circuit design suitable for space ...
- Lorena ANGHEL joins SPINTEC (June 05th, 2020)
We are pleased to announce the arrival on June 1st, 2020 at SPINTEC, within the Spintronics IC design team of Lorena ANGHEL, professor at Grenoble INP / PHELMA, currently deputy director in charge of Research ...