Magnetic memories based on magnetic tunnel junctions, called Spin-Transfer-Torque Random Access Memories (STT-MRAM), are stimulating a considerable interest in microelectronics thanks to their combination of assets: non-volatility, density, speed, endurance. In this work, a new flavor of these memories was developed allowing ultrafast (sub-ns) writing suitable for cache SRAM-type of applications.
Spin-transfer-torque (STT) allows to act on the magnetization of magnetic nanostructures with a spin-polarized electrical current thanks to the exchange interaction between the spin of the conduction electrons and those responsible for the local magnetization. It is now used as a new write scheme in magnetic memories. The storage elements in these memories are magnetic tunnel junctions (MTJs) which comprise two magnetic layers: a storage one and a reference one separated by a thin tunnel barrier, generally of MgO about 1nm thick. The information is coded in the direction of orientation of the storage layer magnetization (MSto) relatively to the reference layer one (MRef)(Parallel (P) or AntiParallel (AP)). These two states are characterized by different electrical resistances due to the tunnel magnetoresistance of MTJs. A problem encountered in conventional STT-MRAM upon writing is that the STT is proportional to MSto^MRef. As a result, departing from an equilibrium state P or AP, the STT is initially zero and one has to wait for a sufficiently strong thermal fluctuations for the STT to become large enough to trigger the magnetization reversal. This slows down the writing process due to the stochasticity of the magnetization switching. To circumvent this issue, SPINTEC has proposed to sandwich the in-plane magnetized storage layer between two polarizing layers of orthogonal magnetizations, one magnetized in-plane as in conventional STT-MRAM, the other magnetized out-of-plane (Fig.a). Thanks to the STT created by the perpendicular polarizer, the STT is non zero from the very onset of the write current pulse. This triggers the magnetization reversal without having to rely on thermal fluctuations. However, the STT from the perpendicular polarizer tends to induce a processional dynamics of the storage layer magnetization and therefore an oscillatory probability of switching versus pulse duration. Controlling the final written state requires to control the pulse duration with a high accuracy of ±50ps which is very difficult to achieve at chip level. Therefore, the relative STT contributions from the two polarizers must be properly tuned to achieve an accurate control of the written final state. We recently demonstrated that this can be achieved by properly adjusting the MTJ cell aspect ratio as shown on the Figure below.
Figure:a) MTJ stack with two orthogonal polarizing layers sandwiching the storage (free) layer. b) Oscillatory switching probability due to dominant role of STT from perpendicular polarizer in low aspect ratio elliptical cells of dimension 80nm*160nm; c) non-oscillatory sub-ns switching probability due to dominant role of in-plane analyzer in cells of large aspect ratio 50nm*250nm.
This work was partially funded by the European Commission through the Adv ERC Project HYMAGINE No. 246942.
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