On wednesday November 29th 2023, we have the pleasure to welcome in SPINTEC Prof. Giovanni Finocchio from University of Messina (Italy) He will give a seminar at 14:30 entitled
New opportunities for spintronic technology from Internet of Things to coprocessors
Place : IRIG/SPINTEC, auditorium 445 CEA Building 10.05 (access to CEA (*))
Visioconference link : https://cnrs.zoom.us/j/91772918635?pwd=RnVqOFRjTURCV094eG90MDFDUVNYUT09
Abstract : The development of more efficient and high performance spintronic devices and the efforts to have cointegration of spintronics with CMOS technology is driving the development of hybrid CMOS-spintronic solutions for application where one can take the advantages of both technologies while minimizing the disadvantages. In this talk, I will focus on our recent developments on new potential applications of magnetic tunnel junctions (MTJs) as compact sensors for IoT nodes and computing applications. I will discuss how MTJs can be used to develop compact and more effective accelerometers and physical unclonable functions for security applications. I will also discuss our recent results on spintronic microwave amplifiers which are based on the phenomenon of injection locking. In this first part of the talk, I will discuss about a single MTJ spinking neuron which does not need any reset mechanism after the spike and it is equivalent in term of behaviour to what described by the Hodgkin-Huxley model. In the second part of the talk I will focus on probabilistic computing with probabilistic-bits (p-bits) which is emerging as a computational paradigm able to be competitive in solving NP-hard combinatorial problems. I will show how to map hard combinatorial optimization problems (Max-Sat, Max-Cut, Traveling Salesman problem) into probabilistic Ising machine by using the idea if invertible logic gates and more complex energy mapping approaches and how to implement those in spintronic and CMOS technology. We will investigate the potential of advanced annealing schemes comparing simulated annealing, parallel-tempering, and simulated-quantum-annealing and how it will possible to implement an efficient probabilistic co-processor.
This work was supported under the project number 101070287 — SWAN-on-chip — HORIZON-CL4- 2021-DIGITAL-EMERGING-01, the project PRIN 2020LWPKH7 funded by the Italian Ministry of University and Research., and by the PETASPIN association (www.petaspin.com). This work has been also partially funded by European Union (NextGeneration EU), through the MUR-PNRR project SAMOTHRACE (ECS00000022).