seminar – Novel information encoding schemes for energy efficient cognitive computing

On Monday, April 29th 2023, we have the pleasure to welcome in SPINTEC Advait Madhavan from University of Maryland. He will give us a seminar at 14:00 entitled :
Novel information encoding schemes for energy efficient cognitive computing

Place : IRIG/SPINTEC, auditorium 445 CEA Building 10.05 (access to CEA requires an entry authorization. Request it before April 19th at

video conference :
try with skype web App :
or by phone +33 1 69 35 55 10 conf ID : 52904673

Abstract : In this talk, I will discuss why energy-efficient acceleration of cognitive-computing tasks in the era of big-data requires simultaneous consideration of multiple levels of the computing stack such as novel information encoding schemes, algorithm-to-architecture mapping, and integration of emerging resistive-switching technologies with CMOS such as magnetic tunnel junctions and memristors. I will illustrate this with three examples of non-Boolean encoding schemes that have been recently researched by my colleagues and I. This includes experimental demonstrations of analog encoding schemes with crossbar arrays of magnetic tunnel junctions for neural network acceleration; probabilistic encoding schemes with a pair of coupled superparamagnetic tunnel junctions for acceleration of combinatorial optimization; and temporal encoding schemes with crossbar arrays of multi-level resistive switches for graph computations.

Biography : Advait Madhavan is an Assistant Research Scientist at the University of Maryland and a Project leader at the Alternative Computing Group at the National Institute of Standards and Technology. After completing his PhD in Electrical and Computer Engineering from the University of California, Santa Barbara he joined the Alternative Computing Group as a postdoctoral researcher. Advait’s research explores novel information encoding schemes for high-performance, data-centric computation with a specific focus on integrating emerging technologies with conventional CMOS chips. His work has received the IEEE MICRO Top Picks award twice, and has been highlighted by Physical Review Journals, Association for Computing Machinery.

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