On August 31, we have the pleasure to welcome Kevin Garello R&D Senior Scientist at IMEC, Belgium. He will give us a seminar which will take place at SPINTEC 434A at 10:15.
SOT-MRAM 300mm integration for low power and ultrafast embedded memories
Microelectronics industry is facing major challenges related to the volatility of CMOS cache memory elements (usually SRAM and eDRAM). Due to decreasing devices size, leakage current in standby mode are now dominating the power dissipation of CMOS circuits. Furthermore, the increased density and reduction in die area lead to heat dissipation and reliability issues. Magnetic RAM (MRAMs) and Spin-Transfer-Torque MRAM (STT-MRAM) are among most credible non-volatile memories candidates that are scalable, low power and fast enough to compete and replace RAM at cache level. Despite all these advantages, STT-MRAM also faces several challenges. The write process is still relatively inefficient and long compared to SRAM. In addition, the high current flowing through the bit cell – magnetic tunnel junction (MTJ) – imposes a severe stress and leads to a time dependent degradation of the MTJ. This usually limits the use of STT-MRAM for low level caches.
Spin-Orbit Torque (SOT) is an alternative spin current source originating from the spin-orbit interaction and mediated by Spin Hall and Rashba effects. SOT distinguishes by offering the possibility to switch magnetization using in-plane currents, unlike STT that requires a current flow in the perpendicular direction through MTJ. Such new memory class, SOT-MRAM[3,4], promise to mitigate above issues: it is a three terminal MTJ-based concept that allows isolating the read and the write path. It result in significant improvement of the read stability, the write speed and the endurance of the device ; therefore opening the path to address SRAM replacement in high cache level by MRAM.
Across the presentation, I will introduce Imec MRAM activities and I will present our recent advances to build and integrate SOT-MTJ cells following industrial processes, using Imec’s 300mm platform. I will report the first successful integration of SOT-MTJ cells on 300 mm wafers using CMOS-compatible processes. Electrical switching, with direct comparison of STT- and SOT-switching operated on same device, reveal that SOT-MRAM is a promising solution for SRAM replacement in cache memory but that some challenges have to be tackled before full integration in future technology nodes can be envisioned.
 C. Chappert et. al, The emergence of spin electronics in data storage, Nature Materials 6, 813–823 (2007)
 I. M. Miron, K. Garello, et. al, Perpendicular switching of a single ferromagnetic layer induced by in-plane current injection , Nature 476, 189 (2011)
 M. Cubukcu, et al., Spin-orbit torque magnetization switching of a three-terminal perpendicular magnetic tunnel junction, Appl. Phys. Lett. 104, 042406 (2014)
 G. Prenat et. al, Ultra-fast and high-reliability SOT-MRAM: From cache replacement to normally-Off computing, IEEE Trans. on Multi-Scale Computing Systems 2 (1), 49-60 (2015)
 K. Garello et. al, VLSI2018 proceedings