For the fabrication of CMOS/MTJ circuits, three different technological lines were developed and made accessible for HYMAGINE purposes.

  1. For simple circuits comprising only a few MTJs interconnected with CMOS transistors, the PTA 400m² upstream research clean-room located in SPINTEC building is used. A MRAM back-end process is operational at PTA and specific process steps required for integration on CMOS wafers (such as CMP) have been developed (see below)
  2. For more complex circuits requiring much higher yield, the CEA/LETI 200mm clean-room was used. There a 200mm magnetic back-end process was developed allowing the deposition and patterning of MTJ stacks above CMOS technology.
  3. For designs taking advantage of the Thermally Assisted writing developed in collaboration with Crocus Technology, the Crocus technology was used in collaboration with their foundry partner (Tower Jazz).
    Here below are a few illustrations of these various technologies :

CMOS/MTJ integration at PTA (simple circuits on 100mm wafers)

Fig.1: General principle of back-end magnetic integration on CMOS technology. Here 1MTJ-1T STT-MRAM cells

Fig.2 : CMP step developed at PTA on top of the CMOS technology to provide flat-enough surface ofr MTJ growth (RMS roughness 0.3nm).

Fig.3: Array of Ta hard mask dots to pattern 100nm magnetic tunnel junctions cells.

Fig.4: Hard mask development for sub-20nm dots. Vertical hard-mask etch achieved with smallest hard mask diameter sizes of 14nm after IBE trimming.

Fig.5: Electrical statistical results on patterned tunnel junction cells on 50mm wafer, showing yields higher than 75% and reaching measured wafer level TMR signal (upstream research PTA technology)

CMOS/MTJ integration at PTA (more complex circuits on 200mm wafers)

Fig: 8 inch toolset available at CEA/LETI for hybrid CMOS/MTJ

Fig: 20mm technology: MTJ integration on CMOS technology at CEA/LETI

Fig: Above IC integration of MTJ for hybrid CMOS/MTJ non-volatile logic at CEA/LETI

Fig: MTJ patterning by ebeam/DUV lithography and IBE with SIMS end point detection at CEA/LETI



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