On Thursday, the 29th Of March 2018 at 14h00, Jyotirmoy CHATTERJEE from LTM & DRF/INAC/SPINTEC, will defend his PhD thesis entitled “Engineering of magnetic tunnel junction stacks for improved STT-MRAM performance and development of novel and cost-effective nano-patterning techniques”
Place : Grenoble INP-PHELMA, Amphitheater M001 – MINATEC Area, Parvis Louis Néel, 38000 Grenoble

Technology-demand for ultra-scaled (sub-20 nm), high-capacity and high-density non-volatile STT-MRAM arrays needs further improvement of thermal stability factor (Δ) with lower critical switching current (Ico) as well as novel cost-effective nano-patterning technology to build more energy efficient memory hierarchy compared to the existing one. In this context, this research work was focused on material optimization and advanced magnetic tunnel junction configurations for (i) enhancement of perpendicular magnetic anisotropy (PMA) and correlatively of the thermal stability factor (Δ) of the memory cells, (ii) reduction of the critical switching current (Ico) of the storage layer magnetization by developing a perpendicular double magnetic tunnel junction (pDMTJ) stack, (iii) realization of an integration friendly thin-pMTJ stack and (iv) demonstrate proofs of concept of novel and cost-effective nano-patterning techniques for high-density memory applications.