Seminar – Computing using magnetic random access memory (CRAM) and spin-orbit torque (SOT) memory cell

On Wednesday September 25 at 11:00 we have the pleasure to welcome Prof. Jian-Ping WANG (University of Minnesota, MN, USA). He will give us a seminar at CEA/IRIG, Bat 1005, room 445 entitled :

Computing using magnetic random access memory (CRAM) and spin-orbit torque (SOT) memory cell

To enable local or edge AI like family-based robots and self-driving cars without using cloud computing, the power consumption for any available computing system is still four to six orders of magnitude higher than needed. This is largely because in modern computing architecture, also named as von Newman architecture, data is fetched from memory, travels through interconnects, is processed in a logic circuit, and is stored back into memory. In contrast, if there was a way to do the computations without the data ever leaving memory, one could simply skip the reading of memory and processing of data, and go directly to processing and storing the results. We proposed a complete new architecture to realize the computation without data transfer between the memory and logic circuit for the first time [1,2]. Our key idea is to directly use the memory cells to carry out the computation [1-3], e.g. compute at the data just mimicking the way our brain operation. We name this new computing architecture as computational random access memory (CRAM) [2]. To realize the computation using memory cells. we proposed and demonstrated a basic concept, voltage controlled logic (VCL). This is a new building block for computation using memory cells. We use MTJs as the basic units. Two parallel connected MTJs with high and low resistance states represent logic ‘1’ and ‘0’ respectively and serve as the two inputs of the NAND operation. The third MTJ at the bottom will act as a detector to detect if the parallel resistance of the two input MTJs is below a certain value and serve as the output of the NAND operation. In the case shown in this figure, the output MTJ is pushed beyond its own critical current and switched to logic ‘1’ as expected for a NAND operation with ‘1’ and ‘0’ input. In this case, the state variable (resistance) is converted to current, which is quasi-linearly combined, and analyzed using the output MTJ as the threshold detector. In previous experiment [1] we showed that there can be sufficient write margin between the input states. This new architecture can be implemented using a variety of available and proposed devices, including magnetic tunnel junctions (MTJs), memristors, all spin-logic devices, or even traditional CMOS based SRAM [2]. Modeling and benchmarking for STT-RAM based CRAM vs other near and in memory computing has been carried out for different applications including bioinformatics computing [4], pattern recognition [5], binary-neural-net-based image classification [6]. Using digit recognition as an example, the energy efficiency could be improved by 40 times and the execution time was improved by 1400 times compared to the latest near memory computing scheme [5].

REFERENCES:
1) A. Lyle, et al, “Direct communication between magnetic tunnel junctions for nonvolatile logic fan-out architecture,” Appl. Phys. Lett., 97 (2010) 152504.
2) J.-P. Wang and J. Harms, “General structure for computational random access memory (CRAM),” U.S. Patent 9224447 B2, 2015.
3) H. Meng, J.G. Wang and J-P Wang, “A spintronics full adder for magnetic CPU”, IEEE Electron Dev. Lett., 26 (2005) 360
4) Z. Chowdhury, et al., “Efficient in-memory processing using spintronics”, Computer Architecture Letters, 17, 1 (2018) 42
5) M. Zabihi, et al, “In-memory processing on the spintronic CRAM: From hardware design to application mapping”, IEEE Transactions on Computers, pp. 1-1. 10.1109/TC.2018.2858251
6) M. Resch, et al, “Exploiting Processing in Non-Volatile Memory for Binary Neural Network Accelerators.” arXiv:1812.03989 (2018).
*This work was partially supported by DARPA Nonvolatile Logic program and NSF NEB and MESEC program.

Biography: Jian-Ping Wang is the Robert F. Hartmann Chair and a Distinguished McKnight University Professor of Electrical and Computer Engineering, and a member of the graduate faculty in Physics, Chemical Engineering and Materials Science and Biomedical Engineering at the University of Minnesota. He received his PhD degree in 1995 from Institute of Physics, Chinese Academy of Sciences, where he performed research on nanomagnetism. He established and managed the Magnetic Media and Materials program at Data Storage Institute, Singapore, as the founding manager, from 1998 to 2002. He joined the faculty of the Electrical and Computer Engineering department at the University of Minnesota in 2002 and was promoted to full professor in 2009. He was the director of the Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN), which consists of 32 professors from 20 US universities. C-SPIN was one of six SRC/DARPA STARnet program centers and the largest vertically integrated research center on spintronic research in the world. Prof. Wang is the director of the Center for Spintronic Materials for Advanced Information Technology (SMART), one of two SRC/NSIT nCORE research centers. He received the information storage industry consortium (INSIC) technical award in 2006 for his pioneering work in exchange coupled composite magnetic media and the outstanding professor award for his contribution to undergraduate teaching in 2010. He is also the recipient of 2019 SRC Technical Excellence Award for his innovations and discoveries in nanomagnetics and novel materials that accelerated the production of magnetic random-access memories. He has authored and co-authored more than 250 publications in peer-reviewed top journals and conference proceedings and holds 42 patents. He is an IEEE fellow.