POST DOC Recruitment on FPGA-based and ASIC-based system level processor architecture development
Context: The last decade has seen the emergence of numerous studies around integrated nanoelectronic
technologies for a growing number of application areas, ranging from the Internet of Things, to integrated
components specialized in the management and optimization of energy consumption, environmental
monitoring, safety and security in the automotive and space industries, support and control in the healthcare
field, and hardware implementations of Artificial Intelligence (AI) algorithms. Today’s mature and emerging
nanoelectronic technologies present a lot of challenges for the design, validation and test of digital and mixedsignal
circuits and architectures. An important aspect of such innovative technologies is their robustness
against attacks, either laser or side-channel attacks, in particular processors for which the integrity has to be
reinforced. Specific studies are mandatory for the most emerging technologies, which is the core of this
project. The project aims to develop a RISC-V architecture with NV MRAM memory elements while ensuring
compliance with security requirements. It will address 3 challenges: 1) the characterization of vulnerabilities
of backup/restore mechanisms in NV processor, 2) the modeling of an innovative Voltage Gated Spin Orbit
Torque (VG-SOT) MRAM cell as elementary cell to build blocks as register and memory and 3) the design of
countermeasures from these blocks to mitigate hardware attacks. To reach these objectives, we will go
through the evaluation of security advances taking profit of MRAM blocks and mitigation mechanisms as
protection schemes at cell level, hardware level and software level. This project endeavors to pioneer a secure,
non-volatile computing paradigm through innovative MRAM integration, addressing critical vulnerabilities and
advancing protection mechanisms, thereby setting a new standard for secure edge computing architectures.
Starting date: October/November 2025
Detailed description: here
To apply: Please send a CV and a letter of motivation to Gregory Di Pendina
