SPINTRONIC IC DESIGN



Research team Spintronic IC design, within the device group


On Monday 9th of Decembre at 13h30 Mounia KHARBOUCHE-HARRARI, will defend her thesis, jointly carried out by IM2NP, CEA-Tech and SPINTEC, entitled : « Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l’Internet des Objets » Place : amphithéâtre HS02 au sein du Campus Georges Charpak Provence, 880 route de Mimet, 13541 Gardanne […]

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Duration : 24 months Beginning: June 2020 Project : NV-APROC funded by the French ANR agency Context : Micro and nano electronics integrated circuit domain is today mainly driven by the advent of the internet of things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the […]

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On Wednesday October 23 at 14:00 we have the pleasure to welcome Maik Wagner-Reetz from Fraunhofer IPMS, Dresden. He will give us a seminar at CEA/SPINTEC, Bat 1005, room 445 entitled : CMOS-compatible materials and processes for spintronic applications in 300mm R&D Spin-based implementations like e.g. Magnetic Random Access Memory (MRAM) or Racetrack Memory (RTM) […]

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On Thursday October 17 at 11:00 we have the pleasure to welcome Julie Grollier from Unité Mixte de Physique CNRS/Thales. She will give us a seminar at CEA/SPINTEC, Bat 1005, room 434A entitled : Dynamics and oscillations in spintronic neural nets The brain displays many features typical of non-linear dynamical networks, such as synchronization or […]

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You find here the list of proposals for Master-2 internships to take place at Spintec during Spring 2020. In most cases, these internships are intended to be suitable for a longer-term PhD work. Interested Master-1 students are also encouraged to apply. You may download the full list of proposals, along with an introduction to the […]

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Spin Orbit Torque Magnetic RAM (SOT-MRAM) approach represents a new way to overcome Spin Transfer Torque (STT) memory limitations by separating the reading and the writing paths. It is particularly interesting for high-speed applications that do not require very high density because of two transistors per bit cell. This work introduces a high-density SOT-MRAM memory […]

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Internet of Things (IoT) applications deployment relies on low-power and security constraints. In this perspective, lightweight cryptography has been developed. This field enables, with a reduced area and power consumption, to encrypt sensitive data processed in an integrated circuit and transmitted to a connected object. This work proposes to implement the PRESENT lightweight cryptographic algorithm […]

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NV-APROC – An ANR project

NV-APROC stands for Non Volatile MRAM-based Asynchronous PROCessor, a 42-month ANR project starting on October 2019, coordinated by Spintec. Micro and nano electronics integrated circuit domain has been strongly driven by the advent of the Internet of Things (IoT). The constraints become very strong, especially in terms of power consumption and autonomy. Therefore there is […]

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MISTRAL – An ANR project

MISTRAL stands for MRAM/CMOS Hybridization to Secure Cryptographic Algorithms, an 42-month ANR project starting on October 2019, coordinated by EMSE (Ecole des Mines de St Etienne in Gardanne). MISTRAL is addressing the security of the cryptography embedded in connected objects at its highest standards while keeping concern by the energy footprint. Consequently, MISTRAL aims at […]

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Rana Alhalabi has been awarded of the best poster prize at the 18th Non-Volatile Memory Technology Symposium that took place in October 2018 in Sendai, Japan. The title of the poster was “High density SOT-MRAM memory array based on a single transistor”. Based on a 32kb memory, this work has shown that replacing one of […]

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