The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications. The unique combination of advantages of spintronics devices (non-volatility associated with high speed and endurance, analogue capabilities, well controlled stochastic behavior…) allows intrinsically mixing the memory and logic functionalities (in Memory Computing). This opens the way towards new computing paradigms, beyond the standard Von-Newman architecture of computing systems. The most interesting applications addressed in the team are described below.
Hybrid CMOS/Magnetic design flow
Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.
Low-power logic circuits
One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.
Spiking Neural Networks are seen as a Key building block for strongly improving the energy efficiency of current AI applications and opening up new possibilities (in terms of unsupervised learning, recurrent networks, probabilistic inference, etc.). The scientific challenges to be tackled are the following: the first one is to define power-constrained learning and inference algorithms (online, supervised, unsupervised, probabilistic, etc.). The second one is to design a scalable and flexible SNN architecture, adaptable to the different above-mentioned algorithms, and fabricate that circuit in hybrid nanoscale CMOS and NVM technology, enabling very dense synaptic density. The last objective is to derive a principled toolchain for the algorithm, design, development, and integration of spiking neural networks for future adoption in industrial health and automotive embedded applications.
IC Reliability : Hardware security
While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.
IC Reliability : Radiation hardening
The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques targeting space applications.
- NV-APROC, ANR (2019-2023) – MRAM-based Non-volatile Asynchronous Processor
- MISTRAL, ANR (2019-2023) – MRAM/CMOS Hybridization to secure cryptographic algorithms
- CARMEM, 80|PRIME – CNRS (2021-2024) – Modèles de Caractérisation par Apprentissage pour la Qualité des Technologies de Mémoires Émergentes
- QUALMEM, ANR (2023-2026) – Quality Assurance of Advanced and Emerging Memory Technologies by Using Machine Learning
- Christophe LAYER : Research scientist
- François DUHEM: Research scientist
- Pablo ILHA VAZ (2022-2022)
- Ghislain TAKAM TCHENDJOU (2020-2021)
- Pierre VANHAUWAERT (2014-2017)
- Eldar ZIANBETOV (2014-2017)
- Kotb JABEUR (2013-2017)
- Virgile JAVERLIAC (2013-2014)
- Fabrice BERNARD-GRANGER (2013-2014)
- Yun YANG (2012-2013)
- Abdelilah MEJDOUBI (2010-2012)
- Odilia COI (supervised by G. Di Pendina, D. Dangla and L. Torres) (2018-2021)
- Antoine HERAUD (supervised by Lorena ANGHEL and Alexandre VALENTIAN) (2020-2022)
- Etienne BECLE (supervised by Lorena ANGHEL, G. PRENAT and I.L. Prejbeanu) (2019-2021)
- Mounia KHARBOUCHE (supervised by G. Di Pendina, R. Wacquez and J.M. Portal) (2016-2019)
- Rana ALHALABI (supervised by G. Di Pendina, E. Nowak and L. Prejbeanu) (2016-2019)
- Jeremy LOPES (supervised by G. Di Pendina, E. Beigne, D. Dangla and L. Torres) (2014-2017)
- Erya DENG (supervised by G. Prenat and L. Anghel) (2014-2017)
- Olivier GONCALVES (supervised by G. Prenat and B. Dieny) (2009-2012)
- Wei GUO (supervised by G. Prenat and B. Dieny) (2006 – 2010)
- Mourad El BARAJI (supervised by G. Prenat and B. Dieny) (2007-2009)
- Stephane GROS (2013-2014)
- Pierre PAOLI (2013-2014)
- SPINBRAIN (2020-2022) – Spintronic-based Neural Network
- HANS, UGA (2019-2022)
- GREAT, H2020 (2016-2019)
- MASTA, ANR (2016-2019)
- ELECSPIN, ANR (2016-2020) – Electric-filed control of spin-based phenomena
- NOVELASIC, CEA-nanosciences (2015)
- MAD, CEA internal (2014-2018)
- SPOT, H2020 (2012-2015)
- MARS, ANR (2012-2015)
- DIPMEM, ANR (2012-2015)
- HYMAGINE, ERC Advanced grant (2010-2015)
- Toplink Innovation
- University of Montpellier
- University of Brasov
- University of Aix-Marseille
- CEA Tech (Gardanne)
- EMSE (Gardanne)
- Tiempo Secure
- Dolphin Integration
- Thales TRT
- University of Newcastle
- EM Marin
- Master students to visit SPINTEC and discuss our topics for internships (September 18th, 2016)
On 25th October 2016 our host Institut INAC welcomes students for a presentation of internship topics proposed to host Master-2 students during Spring 2017. Details will be provided later.
- Research engineer tenure track open position (filled) (July 28th, 2016)
SPINTEC has developed over the last decade many tools for integrating spintronic devices into standard CMOS microelectronics : design tools have been developed and elementary proofs of concept circuits have been built and tested. The integration ...
- GREAT – A H2020 ICT project at SPINTEC (June 30th, 2016)
Overview GREAT (European H2020 project) was accepted at the Summer 2015. Its kick-off meeting took place at SPINTEC in Grenoble on February 22nd-23rd 2016. The project aims at developing magnetic stacks able to equally perform memory, radio-frequency ...