The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications.
Hybrid CMOS/Magnetic design flow
Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.
Low-power logic circuits
One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.
While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.
Radiation hardening for space applications
The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques.
- Kotb JABEUR
- Pierre VANHAUWAERT
- Mounia KHARBOUCHE
- Rana ALHALABI
- Jeremy LOPES
- GREAT, H2020 (2016-2019)
- ANR MASTA (2016-2019)
- Toplink Innovation
- University of Brasov
- PhD defense – Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l’Internet des Objets (November 28th, 2019)
On Monday 9th of Decembre at 13h30 Mounia KHARBOUCHE-HARRARI, will defend her thesis, jointly carried out by IM2NP, CEA-Tech and SPINTEC, entitled : « Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l’Internet des ...
- Postdoc or engineer position in processor design and optimization (November 19th, 2019)
Duration : 24 months Beginning: June 2020 Project : NV-APROC funded by the French ANR agency Context : Micro and nano electronics integrated circuit domain is today mainly driven by the advent of the internet of things for which ...
- Seminar – CMOS-compatible materials and processes for spintronic applications in 300mm R&D (October 21st, 2019)
On Wednesday October 23 at 14:00 we have the pleasure to welcome Maik Wagner-Reetz from Fraunhofer IPMS, Dresden. He will give us a seminar at CEA/SPINTEC, Bat 1005, room 445 entitled : CMOS-compatible materials and processes ...
- Seminar – Dynamics and oscillations in spintronic neural nets (October 03rd, 2019)
On Thursday October 17 at 11:00 we have the pleasure to welcome Julie Grollier from Unité Mixte de Physique CNRS/Thales. She will give us a seminar at CEA/SPINTEC, Bat 1005, room 434A entitled : Dynamics and ...
- Masters thesis projects for Spring 2020 (September 30th, 2019)
You find here the list of proposals for Master-2 internships to take place at Spintec during Spring 2020. In most cases, these internships are intended to be suitable for a longer-term PhD work. Interested Master-1 ...