The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications.

Research topics

Hybrid CMOS/Magnetic design flow


Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.

Low-power logic circuits


One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.

Hardware security


While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.

Radiation hardening for space applications


The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques.

The team

Permanent staff

Guillaume PRENAT

François DUHEM


  • Kotb JABEUR


  • Jeremy LOPES


  • GREAT, H2020 (2016-2019)
  • ANR MASTA (2016-2019)


  • eVaderis
  • TowerJazz
  • Singulus
  • Toplink Innovation
  • TIMA
  • IEF
  • TUD
  • University of Brasov
  • KIT
  • LETI
  • IM2NP

    Recent news

  • The EU GREAT Project delivered its 2nd tape-out demonstrator (October 16th, 2018)
    A full hybrid magnetic/CMOS System on Chip (SoC), embedding analog and digital functions based on spintronics devices on the same die, has been designed and sent to manufacturing. It is the first demonstrator of such ...
  • Masters thesis projects for Spring 2019 (October 10th, 2018)
    You find here the list of proposals for Master-2 internships to take place during Spring 2019. In most cases, these internships are intended to be suitable for a longer-term PhD work. Interested Master-1 students are ...
  • Seminar – NV-RAM and harvesting technologies for next generation sensors: a system and software perspective (October 10th, 2018)
    On October 23 at 11am at SPINTEC room 434A, Guillaume Salagnac (left) and Tanguy Risset (right) from INRIA Lyon will kindly present the work of their team during a seminar entitled: “NV-RAM and harvesting technologies for ...
  • High speed and low area look-up table design based on MRAM memory (September 07th, 2018)
    Continual growth in the size and functionality of FPGA over few years leads to an increasing interest in their use for high speed applications. However, the memory access speed limits the execution speed. The great ...
  • Best poster award of EEATS (June 08th, 2018)
    In the framework of an internal collaborative project between CEA-LETI and CEA/CNRS/UGA-SPINTEC Lab, Rana Alhalabi proposed a new Look Up Table (LUT) architecture, which is one of the elementary cell of FPGAs (Field Programmable Grid ...

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