The team is dedicated to the evaluation of the benefits of using magnetic devices in Integrated Circuits (ICs). It is expected that integrating non-volatility in ICs could contribute to push forward the incoming limits in the microelectronics scaling. This work includes integrating the magnetic devices in standard design tools, design hybrid circuits and evaluate their performance for various applications.

Research topics

Hybrid CMOS/Magnetic design flow


Designing hybrid circuits requires integrating the magnetic devices in the standard design flow of microelectronics. This includes compacts models for electrical simulations, technology files including the magnetic back-end and libraries of Standard Cells for digital design.

Low-power logic circuits


One issue related to microelectronics scaling is the increasing standby power, due to leakage currents. Introducing non-volatility in circuits allows easing the power gating technique, which consists in cutting-off the power supply of inactive blocks to save leakage.

Hardware security


While STT MRAM can be beneficial for hardware security (taking advantage of its stochastic behavior for cryptography for instance), it also presents some specific failures mechanisms that has to be studied to take the appropriate countermeasures.

Radiation hardening for space applications


The intrinsic hardness to radiations of the magnetic devices make them a good candidate to be embedded in circuits for space applications. It can be advantageously combined with other hardening technologies or design techniques.

The team

Permanent staff

Guillaume PRENAT

François DUHEM


  • Kotb JABEUR


  • Jeremy LOPES


  • GREAT, H2020 (2016-2019)
  • ANR MASTA (2016-2019)


  • eVaderis
  • TowerJazz
  • Singulus
  • Toplink Innovation
  • TIMA
  • IEF
  • TUD
  • University of Brasov
  • KIT
  • LETI
  • IM2NP

Recent news

  • Seminar – Dynamics and oscillations in spintronic neural nets (October 03rd, 2019) Seminar - Dynamics and oscillations in spintronic neural nets
    On Thursday October 17 at 11:00 we have the pleasure to welcome Julie Grollier from Unité Mixte de Physique CNRS/Thales. She will give us a seminar at CEA/SPINTEC, Bat 1005, room 434A entitled : Dynamics and ...
  • Masters thesis projects for Spring 2020 (September 30th, 2019) Masters thesis projects for Spring 2020
    You find here the list of proposals for Master-2 internships to take place at Spintec during Spring 2020. In most cases, these internships are intended to be suitable for a longer-term PhD work. Interested Master-1 ...
  • High-density SOT-MRAM memory array based on a single transistor (September 18th, 2019) High-density SOT-MRAM memory array based on a single transistor
    Spin Orbit Torque Magnetic RAM (SOT-MRAM) approach represents a new way to overcome Spin Transfer Torque (STT) memory limitations by separating the reading and the writing paths. It is particularly interesting for high-speed applications that do ...
  • Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis (September 04th, 2019) Light-Weight Cipher Based on Hybrid CMOS/STT-MRAM: Power/Area Analysis
    Internet of Things (IoT) applications deployment relies on low-power and security constraints. In this perspective, lightweight cryptography has been developed. This field enables, with a reduced area and power consumption, to encrypt sensitive data processed in ...
  • NV-APROC – An ANR project (August 12th, 2019) NV-APROC - An ANR project
    NV-APROC stands for Non Volatile MRAM-based Asynchronous PROCessor, a 42-month ANR project starting on October 2019, coordinated by Spintec. Micro and nano electronics integrated circuit domain has been strongly driven by the advent of ...

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